The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of multiple patterning.
As integrated circuit structures continue to shrink, device fabrication techniques are modified and adapted to make devices with increasingly smaller dimensions and increasingly smaller separations (i.e., pitch) between device features. Multiple patterning techniques, such as multiple pattern lithography, are often used to achieve spacing between device features, such as half-pitch spacing or even less, that could not be achieved by other lithography techniques. Such techniques generally include forming mandrel lines at pitch, sometimes referred to as “assist” lines or “dummy” lines, around which are formed sidewall spacers that are then used to pattern the actual desired features at half-pitch or lower into a patternable layer. In many cases, circuit structure designs require cuts or gaps in a single mandrel line or in multiple mandrel lines, in which each cut separates a single mandrel line into two or more mandrel lines.